cmos sram k6t1008c2e family revision 4.0 may 2002 1 document title 128kx8 bit low power cmos static ram revision history revision no. 0.0 1.0 1.01 2.0 3.0 4.0 remark preliminary final final final final history design target finalize - improve t wp form 55ns to 50ns for 70ns product. - remove 55ns speed bin from industrial product. errata correction revise revise - add 55ns parts to industrial products. revise - add automotive temperature products draft data october 12, 1998 august 30, 1999 december 1, 1999 february 14, 2000 march 3, 2000 may 30, 2002 the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserves the right to change the spec ifications and products. samsung electronics will answer to your questions. if you have any questions, please contact the samsung branch office s.
cmos sram k6t1008c2e family revision 4.0 may 2002 2 128kx8 bit low power cmos static ram general description the k6t1008c2e families are fabricated by samsung s advanced cmos process technology. the families support various operating temperature ranges and have various pack- age types for user flexibility of system design. the families also support low data retention voltage for battery back-up operation with low data retention current. features process technology: tft organization: 128k x 8 power supply voltage: 4.5~5.5v low data retention voltage: 2v(min) three state output and ttl compatible package type: 32-dip-600, 32-sop-525, 32-tsop1-0820f/r pin description name function cs 1 , cs 2 chip select input oe output enable input we write enable input i/o 1 ~i/o 8 data inputs/outputs a 0 ~a 16 address inputs vcc power vss ground nc no connection product family 1. the parameters are tested with 50pf test load product family operating temperature vcc range speed power dissipation pkg type standby (i sb1 , max) operating (i cc2, max) k6t1008c2e-l commercial(0~70 c) 4.5~5.5v 55 1) /70ns 50 m a 50ma 32-dip-600, 32-sop-525 32-tsop1-0820f/r k6t1008c2e-b 10 m a k6t1008c2e-p industrial(-40~85 c) 50 m a 32-sop -525 32-tsop1-0820f/r k6t1008c2e-f 15 m a k6t1008c2e-q automotive(-40~125 c) 50 m a 32-sop -525 functional block diagram samsung electronics co., ltd. reserves the right to change products and specifications without notice. precharge circuit. memory array 1024 rows 128 8 columns i/o circuit column select clk gen. row select i/o 1 data cont data cont i/o 8 cs 1 we oe cs 2 control logic a11 a9 a8 a13 we cs2 a15 vcc nc a16 a14 a12 a7 a6 a5 a4 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 vss i/o3 i/o2 i/o1 a0 a1 a2 a3 type1-forward 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 nc a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 cs2 we a13 a8 a9 a11 oe a10 cs 1 i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-dip 32-tsop 32-sop column address raw address a4 a5 a6 a7 a12 a14 a16 nc vcc a15 cs2 we a13 a8 a9 a11 a3 a2 a 1 a0 i/o1 i/o2 i/o3 vss i/o4 i/o5 i/o6 i/o7 i/o8 cs 1 a10 oe type1-reverse 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 32-tsop
cmos sram k6t1008c2e family revision 4.0 may 2002 3 product list commercial temp. products(0~70 c) industrial temp. products(-40~85 c) automotive temp. products(-40~125 c) part name function part name function part name function k6t1008c2e-dl55 k6t1008c2e-dl70 k6t1008c2e-db55 k6t1008c2e-db70 k6t1008c2e-gl55 k6t1008c2e-gl70 k6t1008c2e-gb55 k6t1008c2e-gb70 k6t1008c2e-tb55 k6t1008c2e-tb70 k6t1008c2e-rb55 k6t1008c2e-rb70 32-dip, 55ns, l pwr 32-dip, 70ns, l pwr 32-dip, 55ns, ll pwr 32-dip, 70ns, ll pwr 32-sop, 55ns, l pwr 32-sop, 70ns, l pwr 32-sop, 55ns, ll pwr 32-sop, 70ns, ll pwr 32-tsop-f, 55ns, ll pwr 32-tsop-f, 70ns, ll pwr 32-tsop-r, 55ns, ll pwr 32-tsop-r, 70ns, ll pwr k6t1008c2e-gp55 k6t1008c2e-gp70 k6t1008c2e-gf55 k6t1008c2e-gf70 k6t1008c2e-tf55 k6t1008c2e-tf70 k6t1008c2e-rf55 k6t1008c2e-rf70 32-sop, 55ns, l pwr 32-sop, 70ns, l pwr 32-sop, 55ns, ll pwr 32-sop, 70ns, ll pwr 32-tsop-f, 55ns, ll pwr 32-tsop-f, 70ns, ll pwr 32-tsop-r, 55ns, ll pwr 32-tsop-r, 70ns, ll pwr k6t1008c2e-gq55 k6t1008c2e-gq70 32-sop, 55ns, l pwr 32-sop, 70ns, l pwr functional description 1. x means don t care (must be in high or low states) cs 1 cs 2 oe we i/o mode power h x 1) x 1) x 1) high-z deselected standby x 1) l x 1) x 1) high-z deselected standby l h h h high-z output disabled active l h l h dout read active l h x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to 7.0 v - voltage on vcc supply relative to vss v cc -0.5 to 7.0 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c k6t1008c2e-l/-b -40 to 85 c k6t1008c2e-p/-f -40 to 125 c k6t1008c2e-q
cmos sram k6t1008c2e family revision 4.0 may 2002 4 recommended dc operating conditions 1) note: 1. commercial product: t a =0 to 70 c industrial product: t a =-40 to 85 c automotive product t a =-40 to 125 c, otherwise specified. 2. overshoot: vcc+3.0v in case of pulse width 30ns. 3. undershoot: -3.0v in case of pulse width 30ns. 4. overshoot and undershoot are sampled, not 100% tested. item symbol product min typ max unit supply voltage vcc k6t1008c2e family 4.5 5.0 5.5 v ground vss all family 0 0 0 v input high voltage v ih k6t1008c2e family 2.2 - vcc+0.5 2) v input low voltage v il k6t1008c2e family -0.5 3) - 0.8 v capacitance 1 ) (f=1mhz, ta=25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 6 pf input/output capacitance c io v io =0v - 8 pf dc and operating characteristics 1. 50 m a for low power product, in case of low low power products are comercial=10 m a, industrial=15 m a. item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs 1 =v ih or cs 2 =v il or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs 1 =v il , cs 2 =v ih, v in =v ih or v il , read - - 10 ma average operating current i cc1 cycle time=1 m s, 100%duty, i io =0ma, cs 1 0.2v, cs 2 3 vcc-0.2v, v in 0.2v or v in 3 v cc -0.2v - - 7 ma i cc2 cycle time=min, 100% duty, i io =0ma, cs 1 =v il , cs 2 =v ih, v in =v ih or v il - - 50 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current(ttl) i sb cs 1 =v ih , cs2=v il , other inputs=v ih or v il - - 3 ma standby current(cmos) i sb1 cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v or cs 2 0.2v, other inputs=0~vcc - - 50 1) m a
cmos sram k6t1008c2e family revision 4.0 may 2002 5 ac characteristics (v cc =4.5~5.5v, commercial product: t a =0 to 70 c, industrial product: t a =-40 to 85 c, automotive product: t a =-40 to 125 c ) parameter list symbol speed bins units 55ns 70ns min max min max read read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select to output t co - 55 - 70 ns output enable to valid output t oe - 25 - 35 ns chip select to low-z output t lz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 20 0 25 ns output disable to high-z output t ohz 0 20 0 25 ns output hold from address change t oh 10 - 10 - ns write write cycle time t wc 55 - 70 - ns chip select to end of write t cw 45 - 60 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 45 - 60 - ns write pulse width t wp 40 - 50 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 20 0 25 ns data to write time overlap t dw 20 - 25 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns c l 1) 1. including scope and jig capacitance ac operating conditions test conditions ( test load and input/output reference) input pulse level: 0.8 to 2.4v input rising and falling time: 5ns input and output reference voltage:1.5v output load(see right): c l =100pf+1ttl c l =50pf+1ttl data retention characteristics 1. cs 1 3 vcc-0.2v, cs 2 3 vcc-0.2v( cs 1 controlled) or cs 2 0.2v(cs 2 controlled) item symbol test condition min typ max unit vcc for data retention v dr cs 1 3 vcc-0.2v 1) 2.0 - 5.5 v data retention current i dr vcc=3.0v, cs 1 3 vcc-0.2v 1) k6t1008c2e-l - - 20 m a k6t1008c2e-b - - 10 k6t1008c2e-p - - 25 k6t1008c2f-f - - 10 k6t1008c2f-q - - 25 data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
cmos sram k6t1008c2e family revision 4.0 may 2002 6 address data out previous data valid data valid timing diagrams timing waveform of read cycle(1) (address controlled , cs 1= oe =v il , cs2= we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs 1 address oe data ou t notes ( read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. cs 2 t oh t aa t olz t lz t ohz t hz(1,2) t rc t co2 t oe t co1
cmos sram k6t1008c2e family revision 4.0 may 2002 7 timing waveform of write cycle(2) ( cs 1 controlled) address cs 1 t wc t wr(4) t as(3) t dw t dh data valid we data in data out high-z high-z cs 2 t cw(2) t wp(1) t aw timing waveform of write cycle(1) ( we controlled) address cs 1 t cw(2) t wr(4) cs 2 t cw(2) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t wc t aw t as(3)
cmos sram k6t1008c2e family revision 4.0 may 2002 8 data retention wave form cs 1 controlled v cc 4.5v 2.2v v dr cs 1 gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr timing waveform of write cycle(3) (cs 2 controlled) address cs 1 t aw notes (write cycle) 1. a write occurs during the overlap of a low cs 1 , a high cs 2 and a low we . a write begins at the latest transition among cs 1 goes low, cs 2 going high and we going low: a write end at the earliest transition among cs 1 going high, cs 2 going low and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs 1 going low or cs 2 going high to the end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs 1 or we going high t wr2 applied in case a write ends as cs 2 going to low. cs 2 t cw(2) we data in data valid data out high-z high-z t cw(2) t wr(4) t wp(1) t dw t dh t as(3) t wc cs 2 controlled v cc 4.5v 0.4v v dr cs 2 gnd data retention mode t sdr t rdr cs 2 0.2v
cmos sram k6t1008c2e family revision 4.0 may 2002 9 package dimensions units: millimeters(inches) 0~15 1.91 #1 32 dual inline package (600mil) #32 13.60 0.20 0.535 0.008 41.91 0.20 1.650 0.008 ( ) 0.075 1 5 . 2 4 0 . 6 0 0 + 0.10 max 42.31 1.666 0.25 - 0.05 + 0.004 0.010 - 0.002 2.54 0.100 max 3.81 0.20 0.150 0.008 5.08 0.200 min 0.015 0.38 0.130 0.012 3.30 0.30 #16 #17 1.52 0.10 0.060 0.004 0.46 0.10 0.018 0.004 32 plastic small outline package (525mil) 0~8 #32 20.47 0.20 0.806 0.008 max 20.87 0.822 max 2.74 0.20 0.108 0.008 3.00 0.118 min 0.002 0.05 0.004 max 0.10 max #1 0.71 ( ) 0.028 1 3 . 3 4 0 . 5 2 5 11.43 0.20 0.450 0.008 0.80 0.20 0.031 0.008 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 14.12 0.30 0.556 0.012 #17 #16 1.27 0.050 + 0.100 0.41 - 0.050 + 0.004 0.016 - 0.002
cmos sram k6t1008c2e family revision 4.0 may 2002 10 32 pin thin small outline package type i (0820f) #32 1.00 0.10 0.039 0.004 max 8.40 0.331 0 . 1 0 m a x 0 . 0 0 4 m a x #1 0.50 ( ) 0.020 18.40 0.10 0.724 0.004 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 #17 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16 package dimensions units: millimeters(inches) 32 thin small outline package type i (0820r) #32 1.00 0.10 0.039 0.004 m a x 8 . 4 0 0 . 3 3 1 0 . 0 0 4 m a x 0 . 1 0 m a x #1 0.50 ( ) 0.020 18.40 0.10 0.724 0.004 0.45 ~0.75 0.018 ~0.030 20.00 0.20 0.787 0.008 #17 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 0~8 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 0.50 0.0197 0.25 ( ) 0.010 min 0.05 0.002 max 1.20 0.047 8 . 0 0 0 . 3 1 5 typ 0.25 0.010 #16
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